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Preliminary W83178S 100 MHZ 3-DIMM SDRAM BUFFER
1. GENERAL DESCRIPTION
The W83178S is a 13 outputs SDRAM clock buffer for 3-DIMMs models incorporate with W83196S14 which is the clock synthesizer especially for the 100 MHz models such as Intel BX chipsets. (Refer the datasheet fo Winbond W83196S-14) The W83178S receives the clock from chipset by the Buffer_In pin and provides almost zero-delay (less than 4 nS propagation delay) SDRAM buffer outputs for the 13 SDRAM clocks which are synchronous with the CPU clock outputs priovided by W83196S-14. The clock skew between any two clock outputs is less than 250 pS and the output buffer impedance is about 15 ohms. The W83178S also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs.
2. FEATURES
* Supports Intel Pentium II CPUs for BX chipset * 13 SDRAM clocks for 3-DIMMs * Clock skew less than 250 pS * Almost none delay Buffer-in controlling SDRAM clocks(<4 nS propagation delay) * I2C 2-wire serial interface * Programmable registers to enable/stop each output * Incorporate with W83196S-14 * Packaged in 28-pin SOP
3. PIN CONFIGURATION
VDD SDRAM 0 SDRAM 1 Vss VDD SDRAM 2 SDRAM 3 Vss BUFFER_IN SDRAM 4 SDRAM 5 SDRAM12 VDD *SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD SDRAM11 SDRAM10 Vss VDD SDRAM 9 SDRAM 8 Vss VDD SDRAM 7 SDRAM 6 Vss Vss *SCLOCK
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Publication Release Date: March 1999 Revision A1
Preliminary W83178S
4. BLOCK DIAGRAM
SDATA SCLK Serial port device Control SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 Buffer_In SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12
5. PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin * - Internal 250K pull-up SYMBOL SDRAM [ 0:12] PIN 2, 3, 6, 7, 10, 11, 12, 18, 19, 22, 23, 26, 27 14 15 9 1, 5, 13, 20, 24, 28 4, 8, 16, 17, 21, 25 I/O O FUNCTION SDRAM clock outputs which have the same frequency as CPU clocks. Serial data of I2C 2-wire control interface Serial clock of I2C 2-wire control interface Clock Input from the chipset Power supply Circuit ground
*SDATA *SDCLK BUFFER_IN VDD Vss
I/O IN IN -
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Preliminary W83178S
6. FUNCTIONAL DESCRIPTION
6.1 2-Wire I2C Control Interface
The clock generator is a slave I2C component which can be read back the data stored in the latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. On power up, the W83178S initializes with default register settings, and then it'optional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-tohigh transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated. Byte writing starts with a start condition followed by 7-bit slave address and [1101 0010], command code checking [0000 0000], and byte count checking. After successful reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to write to internal I2C registers after the string of data. The sequence order is as follows: Bytes sequence order for I2C controller:
Clock Address A(6:0) & R/W
Ack
8 bits dummy Command code
Ack
8 bits dummy Byte count
Ack
Byte0,1,2... until Stop
Set R/W to 1 when read back the data sequence is as follows:
Clock Address A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4... until Stop
6.2 Serial Control Registers
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged. 6.2.1 Register 0: (1 = Active, 0 = Inactive) BIT 7 6 5 4 3 2 1 0 @POWERUP 1 1 1 1 1 1 PIN 11 10 7 6 3 2 DESCRIPTION SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved Reserved SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Publication Release Date: March 1999 Revision A1
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Preliminary W83178S
6.2.2 Register 1: (1 = Active, 0 = Inactive) BIT 7 6 5 4 3 2 1 0 @POWERUP 1 1 1 1 1 1 1 1 PIN 27 28 23 22 19 18 DESCRIPTION SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved Reserved SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive)
6.2.3 Register 2: (1 = Active, 0 = Inactive) BIT 7 6 5 4 3 2 1 0 @POWERUP x 1 x x x x x x PIN 12 Reserved SDRAM12 (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved DESCRIPTION
7.0 SPECIFICATIONS
7.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). PARAMETER Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature SYMBOL VDD, VIN TSTG TB TA RATING -0.5V to +7.0V -65 C to +150 C -55 C to +125 C 0 C to +70 C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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Preliminary W83178S
7.2 AC Characteristics
VDD = 3.3V 5 % , TA = 0 C to +70 C, Test load = 30 pF
PARAMETER Input Frequency Output Rise Time Output Fall Time Output Skew, Rising Edges Output Skew, Falling Edges Output Enable Time Output Disable Time Rising Edge Propagation Delay Falling Edge Propagation Delay Duty Cycle AC Output Impedance
SYM. FIN TR TF TSR TSF TEN TDIS TPR TPF TD ZO
MIN. 0 1.5 1.5
TYP.
MAX. 150 4.0 4.0 250 250
UNITS MHz V/nS V/nS pS pS nS nS nS nS %
TEST CONDITIONS Measured from 0.4V to 2.4V Measured from 0.4V to 2.4V
1.0 1.0 1.0 1.0 45 15
8.0 8.0 <4.0 <4.0 55
Measure at 1.5V
7.3 DC Characteristics
VDD = 3.3V 5 %, TA = 0 C to +70 C
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current, BUFFER_IN Input Leakage Current Output Low Voltage Output High Voltage Output Low Current Output High Current Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
SYM. VIL VIH IIL IIL VOL VOH IOL IOH CIN COUT LIN
MIN. Vss -03 2.0 -5 -20
TYP.
MAX. 0.8 VDD +0.5 +5 +5 50
UNITS Vdc Vdc A A mVdc Vdc mA mA pF pF nH
TEST CONDITIONS
IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V
3.1 65 70 100 110 160 185 5 6 7
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Publication Release Date: March 1999 Revision A1
Preliminary W83178S
8. ORDERING INFORMATION
PART NUMBER W83178S PACKAGE TYPE 28-pin SOP PRODUCTION FLOW Commercial, 0 C to +70 C
9. HOW TO READ THE TOP MARKING
W83178S 28051234 814GBB
1st line: Winbond logo and the type number: W83178S 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR BB: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Preliminary W83178S
10. PACKAGE DIMENSIONS
28-pin SOP
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date: March 1999 Revision A1

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